1. Field of the Invention
The present invention relates to a method of manufacturing a liquid crystal display unit; and more particularly, the present invention relates to a method of manufacturing a liquid crystal display unit for use in a liquid crystal display.
2. Descriptions of the Related Art
Conventionally, thin-film transistor liquid crystal displays (TFT-LCDs) have had inadequate brightness levels and a high power consumption of backlight sources thereof One of the parameters that affect the light emission of an LCD is the aperture ratio of pixels, which is defined as the ratio of a light-transmissive area to the pixel area of a pixel. Accordingly, the design of the pixel aperture ratio has a direct influence on both the utilization of the backlight source and the brightness of the LCD. Therefore, over recent years, it is important to improve the aperture ratio (i.e., how to increase the aperture ratio) of a pixel. New technologies for improving the aperture ratio of an LCD are also being developed in this field to obtain an LCD with low power consumption but a high brightness.
In the design of a TFT-LCD, a conventional method for increasing the aperture ratio is to enlarge the area of the pixel electrode (typically a transparent conductive electrode made of, e.g., Indium Tin Oxide) and have it overlapped with the source/drain circuit. This may lead to an increase of about 10%˜20% in the aperture ratio. However, this makes the pixel electrode closer to the data line. If the pixel electrode is disposed too close to the data line, a capacitor Cpd with excessive parasitic capacitance would be formed therebetween. The impact of the parasitic capacitor Cpd will be further described hereinbelow.
In typical TFT elements, a dielectric material of a relatively high dielectric constant (e.g., a SiNx film) is often provided between the pixel electrode and the data line. The relatively high dielectric constant may cause an increase in the Cpd. If the capacitance value of the parasitic capacitor Cpd goes excessively high, the fully charged pixel electrode may incur cross talk prior to transitioning to the next frame under the influence of different voltages transferred on the data line. The electrical characteristics brought about by the cross talk may cause error in the output, and the consequent parasitic effect may seriously impair the integrity of the signals, causing error in the image displayed and poorer display quality of the TFT-LCD.
Up to now, a number of methods for mitigating the effect of the parasitic capacitor Cpd have been proposed in this field, one of which is illustrated in FIG. 1. As shown, a common electrode line 103, a dielectric layer 105, a data line 107, a passivation layer 109 and a pixel electrode 111 are disposed on the substrate 101. A storage capacitor Cs is formed between the common electrode line 103 and the pixel electrode 111. A parasitic capacitor Cpd exists between the pixel electrode 111 and the data line 107. The passivation layer 109 in this structure enlarges the distance between the common electrode line 103 and the pixel electrode 111 to weaken the effect of the parasitic capacitor Cpd.
However, the structure illustrated in FIG. 1 also leads to an enlarged distance between the common electrode line 103 and the pixel electrode 111. Consequently, the storage capacitor Cs between the common electrode line 103 and the pixel electrode 111 is decreased in value, which necessitates the enlargement of the surface area of the electrodes associated with the storage capacitor for the total storage capacitor Cst to remain unchanged. As a result, the enlargement of the electrode surface area implies a decrease in the aperture ratio. Furthermore, the additional passivation layer 109 renders the manufacturing process more complex and adds to the production cost. In a specific embodiment of this method, the resulting black matrix (not shown) above the data line 107 has a width larger than 20 micrometers (μm).
Alternatively, a consistent electric field shield may be provided between the pixel electrode and the data line to decrease the parasitic capacitance therebetween. In typical shielding approaches, a metal shield is often used to clad the conductive line in expectation of an electric field shielding effect. However, because the metal shield is disposed too close to the conductive lines, charge accumulation tends to occur on the metal shield due to the electric field coupling between the metal shield and the conductive line. Hence, the metal shield has to be grounded or connected to a constant voltage to obviate the charge accumulation thereon while still serving a shielding function.
FIG. 2 depicts a structure with a metal shield and a high aperture ratio. In this structure, a first insulating layer 203, a second insulating layer 205, a data line 207, a third insulating layer 209, a pixel electrode 211, and a storage electrode 213 are disposed on a substrate 201. The storage electrode 213, which is at a common potential, is interposed between the data line 207 and the pixel electrode 211 and configured to shield the effect of the parasitic capacitor Cpd between the data line 207 and the pixel electrode 211. This method imposes less impact on the aperture ratio, and in the specific embodiment of this method, the width of the resulting black matrix (not shown) above the data line 207 is decreased to 10 μm. However, as compared to typical pixel structures, this method requires an additional insulating layer and an additional metal layer to shield the electrode. This renders the manufacturing process more complex and adds to both the production duration and cost.
There are also other means for decreasing the parasitic capacitor Cpd. For example, the storage capacitor can be increased to decrease the proportion of the parasitic capacitor Cpd that accounts for the total capacitor Ctotal of a sub-pixel unit. However, if the storage capacitor is to be increased in size, the area of the opaque electrodes associated with the storage capacitor has to be increased, which will adversely affect the aperture ratio. Another method is to coat a low-k organic insulator film (K=2.7˜3.5) on appropriate locations through a photo-imaging and an SOG process to weaken the effect of the parasitic capacitor between the data line and the pixel electrode or even to overlap the pixel electrode with the data line. However, the drawbacks of the low-k organic insulator film such as water absorption, yellowed and poor interface adhesion may have an adverse impact on the production yield and throughput. Alternatively, during the design of the pixel, a distance larger than a certain value may be kept between the pixel electrode and the data line. However, the aperture ratio is compromised as the distance gets larger, although the effect of the parasitic capacitor Cpd is weakened accordingly.
Although the aforesaid methods may weaken the effect of the parasitic capacitor Cpd, there are still many drawbacks. For example, they have adverse impact on the aperture ratio, render the manufacturing process complex, and add to both production time and cost. Therefore, it is still important to overcome the effect of the parasitic capacitor Cpd between the data line and the pixel electrode. In view of this, it is highly desirable in the art to provide a method for manufacturing a liquid crystal display unit that can weaken the effect of the parasitic capacitor Cpd.